Schottky barrier tunnel transistor and method for fabricating the same

ABSTRACT

A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present invention claims priority of Korean patent applicationnumber 10-2006-0118986 filed on Nov. 29, 2006, which is incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method forfabricating the same, more particularly, to a Schottky barrier tunneltransistor and a method for fabricating the same.

Advancement in semiconductor technology and equipment leads tofabrication of transistors with a short channel of 100 nanometers (nm)or less. Devices following the typical simple electrical physical lawsaccompany quantum mechanical phenomena. A single electron transistor(SET) is one representative example for such devices.

A conventional structure of the SET usually uses a barrier that isgenerated by forming a pattern in an artificial shape over asilicon-based structure using a difference in an oxidation rate relyingon a pattern. This characteristic may worsen an operationalcharacteristic of a device in view of the Moore's law.

In a transistor with a channel length less than 100 nm, leakage currentis likely to occur due to a short channel effect. Thus, an appropriatecontrol is generally required. In an attempt to suppress the shortchannel effect, the junction depth of a source and a drain needs to bein a range of ⅓ to ¼ of the channel length. Although many researchersput an effect to form a shallow junction with low accelerating voltagewhile continuously using an ion implantation, Implemented typically insemiconductor fabrication processes, it is often difficult to controlthe junction depth of the source and the drain to be shallow and uniformbelow 30 nm. Thus, one suggested method is to diffuse impurity ionsusing a rapid thermal process (RTP), a laser annealing process, or asolid phase diffusion (SPD) process. However, this impurity iondiffusion method may be limited to obtain a junction depth of 10 nm orless. Furthermore, as the junction depth decreases, parasitic resistancecomponents of the source and drain including a source-drain extensionregion caused by the diffusion of the impurity ions increase. Based onthis relationship, in the assumption that a doping concentration is1×10¹⁹ atoms/cm³ and a junction depth is 10 nm, a sheet resistance is500 ohms (Ω)/sq. or more. This value exceeds a sheet resistance of about300 (Ω)/sq. proposed by the international technology roadmap forsemiconductor (ITRS), and may cause a limitation such as signal delay.

In addition to the implementation of the shallow junction depth of thesource and drain, permittivity of a gate insulation layer (e.g., oxide)needs to increase to suppress the short channel effect. Many researcheshave been done to replace a silicon oxide layer, which is typically usedin these days, with an oxide layer containing a rare earth metal of ahigh dielectric constant. However, as compared with the silicon oxidelayer, the rare earth metal-based oxide layer may not be effectivelyheat treated due to its thermal instability. Therefore, a heat treatmentin semiconductor processes needs to be performed at low temperature touse such a rare earth metal-based oxide layer. In that case, a heattreatment that proceeds after the ion implantation to activate ions andrecover crystal damage may be performed with some limitations.

For the minimization of metal oxide semiconductor field effecttransistors (MOSFETs), those limitations associated with a gate oxidematerial and shallow junctions between source-drain regions and channelsneed to be overcome in respect of the short channel effect. One proposedapproach is Schottky barrier tunnel transistor (SBTT) technology. Indetail, source and drain regions of MOSFETs are replaced with a metal orsilicide. As compared with the conventional MOSFETs, the sheetresistance measured when the SBTT technology is employed decreases by1/10-fold to 1/50-fold. Thus, an operation speed can be improved, and achannel length can decrease to 35 nm or less. Also, since an ionimplantation is not necessary, a subsequent heat treatment is also notnecessary. As a result, a process for fabricating devices using a gateoxide layer based on a high-K dielectric material can be co-used in theSBTT technology. As compared with the conventional MOSFET technology,even though the subsequent heat treatment is implemented, the heattreatment is performed at low temperature. Thus, a process of forminggates based on a metal can be co-used in the SBTT technology.

FIG. 1 illustrates a cross-sectional view of a conventional SBTTstructure. The SBTT includes: a substrate 10; a buried oxide layer 11formed on the substrate 10; source and drain regions 12 formed inside asilicon-on-insulator (SOI) substrate, which is formed on the buriedoxide layer 11; a gate insulation layer 13 formed on a channel region 16of the SOT substrate; a gate electrode 14 formed on the gate insulationlayer 13; and spacers 15 formed on both sidewalls of the gate electrode14.

The conventional SBTT is formed to have a vertical structure in whichthe gate insulation layer 13 and the gate electrode 14 are formed insequence on the SOI substrate. The conventional SBTT structure issimilar to the conventional MOSFET structure. Different from theconventional MOSFET fabrication process, the source and drain regions 12in the SBTT structure are not formed by the ion implantation but usuallyby a sputtering method. Based on the sputtering method, a thin metalfilm is first deposited, and heat treated to form a silicide layer.

However, since the conventional SBTT has a structure in which the gateinsulation layer is interposed underneath the gate electrode, inconsideration of the short channel effect, the gate insulation layer maybe formed of a high-K dielectric material-based thin film, or thethickness of the gate insulate layer needs to be reduced. In the case ofusing polysilicon as a gate electrode material, an effective oxidethickness increases due to a depletion effect observed between the gateelectrode and the gate insulation layer. In particular, the conventionalSBTT technology may have a difficulty in satisfying a required effectiveoxide thickness of 1.5 nm or less in a device with a line width of 50 nmor less. Also, among high-K dielectric thin films, it may still bedifficult to develop a thin film that can have a stable effectiveinsulation thickness of 2 nm or less.

SUMMARY OF THE INVENTION

Specific embodiments of the present invention are directed towardproviding a Schottky barrier tunnel transistor capable of suppressing ashort channel effect with a simple structure.

Specific embodiments of the present invention are directed towardproviding a method for fabricating a Schottky barrier tunnel transistorthrough a simplified process.

In accordance with one aspect of the present invention, there isprovided a Schottky barrier tunnel transistor. The Schottky barriertunnel transistor includes a gate electrode formed over a channel regionof a substrate to form a Schottky junction with the substrate, andsource and drain regions formed in the substrate exposed on both sidesof the gate electrode.

In accordance with another embodiment of the present invention, there isprovided a method for fabricating a Schottky barrier tunnel transistor.The method includes forming a gate electrode over a channel region of asubstrate, the gate electrode providing a Schottky junction with thesubstrate, forming spacers over sidewalls of the gate electrode, andforming source and drain regions in the substrate exposed on both sidesof the spacers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a conventional Schottkybarrier tunnel transistor (SBTT).

FIG. 2 illustrates a cross-sectional view of a SBTT in accordance withan embodiment of the present invention.

FIGS. 3A to 3D are cross-sectional views illustrating a method forfabricating a SBTT in accordance with an embodiment of the presentinvention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 2 illustrates a cross-sectional view of a Schottky barrier tunneltransistor (SBTT) in accordance with an embodiment of the presentinvention. In the following drawings, the thickness of layers andregions are exaggerated for clarity of the description, and when it isdescribed that one layer is formed on another layer or a substrate, theterm “on” indicates that the layer may be formed directly on the otherlayer or the substrate, or a third layer may be interposed therebetween.

The SBTT includes a silicon-based substrate 112, a gate electrode 113,and source and drain regions 115. The gate electrode 113 is formed overa channel region of the silicon-based substrate 112, so as to form aSchottky junction with the silicon-based substrate 112. The source anddrain regions 115 are formed inside the silicon-based substrate 112exposed on both sides of the gate electrode 113, and include silicide.

The silicon-based substrate 112 includes the channel region, and may bea silicon-on-insulator (SOI) substrate or a bulk substrate, which has alow unit cost. For instance, in the case of fabricating a P-type devicein which holes function as carriers, the silicon-based substrate 112 isdoped with a P-type impurity ion including a group III element such asboron (B). In the case of fabricating an N-type device in whichelectrons function as carriers, the silicon-based substrate 112 is dopedwith an N-type impurity ion including a group V element such asphosphorus (P) or arsenic (As). A concentration of such an impurity ionis low being about 10¹⁷ atoms/cm³ or less. The silicon-based substrate112 is formed as thin as possible. For instance, a thickness of thesilicon-based substrate 112 may be about 100 nm or less. Morespecifically, the silicon-based substrate 112 is formed to a thicknessthat allows control of an electric field that a gate controls. Thus, thethickness of the channel region that the gate controls decreases, sothat formation of an inversion layer can be easily controlled. As aresult, leakage current usually generated between the source and drainregions 115 can be reduced.

The gate electrode 113 directly contacts the channel region, therebyforming a Schottky junction with the silicon-based substrate 112. Thegate electrode 113 may include a metal-based layer or a metalsilicide-based layer, which is a conjugate material between a metal andsilicon. For example, the metal-based layer may include a transitionmetal or rare earth metal. The transition metal may include one selectedfrom a group consisting of iron (Fe), cobalt (Co), tungsten (W), nickel(Ni), palladium (Pd), platinum (Pt), molybdenum (Mo), and titanium (Ti).The rare earth metal may include one selected from a group consisting oferbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), lanthanum (La),cerium (Ce), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm),and lutetium (Lu).

As similar to the gate electrode 113, the source and drain regions 115may include a metal-based layer or a metal silicide-based layer. Themetal-based layer may include a transition metal or a rare earth metal,and the metal silicide-based layer may include a conjugate materialbetween a metal and silicon. More specifically, the source and drainregions 115 include metal silicide, which is a conjugate materialbetween a rare earth metal and silicon.

A method for fabricating the SBTT illustrated in FIG. 2 will bedescribed in detail. FIGS. 3A to 3D are cross-sectional viewsillustrating the SBTT fabrication method in accordance with anembodiment of the present invention.

Referring to FIG. 3A, a SOI substrate includes a support substrate 210,a buried oxide layer 211, and a silicon-based substrate 212. Instead ofthe SOI substrate, a bulk substrate may be used. An ion implantation forforming a well and another ion implantation for adjusting a thresholdvoltage are performed. For instance, for the ion implantation forforming the well, when a P-type device is to be fabricated, thesilicon-based substrate 212 is doped with a P-type impurity ion such asboron. On the other hand, when an N-type device is to be fabricated, thesilicon-based substrate 212 is doped with an N-type impurity ion such asphosphorus or arsenic, which is a group V element. A concentration ofthe impurity ion doped into the silicon-based substrate 212 is low beingabout 10¹⁷ atoms/cm³ or less.

Prior to or after performing the ion implantation for forming the well,the silicon-based substrate 212 is dry etched such that a certainportion of the silicon-based substrate 212 remains over the buried oxidelayer 211. One remaining portion of the silicon-based substrate 212becomes a channel region, and another remaining portion thereof becomessource and drain regions 215 (see FIG. 3D).

Referring to FIG. 3B, a gate electrode 213 is formed over a channelregion of the silicon-based substrate 212. The gate electrode 213includes a metal-based layer or a metal silicide-based layer, which isformed of a conjugate material of a metal and silicon. For instance, themetal-based layer may include a transition metal or a rare earth metal.The transition metal may include one selected from a group consisting ofFe, Co, W, Ni, Pd, Pt, Mo, and Ti. The rare earth metal may include oneselected from a group consisting of Er, Yb, Sm, Y, La, Ce, Tb, Dy, Ho,Tm, and Lu.

In the case of fabricating an N-type device, the gate electrode 213 mayinclude Pt, which provides a high Schottky barrier to electrons, orplatinum silicide. In the case of fabricating a P-type device, the gateelectrode 213 may include erbium silicide, which provides a highSchottky barrier to holes.

A method of forming the gate electrode 213 based on a metal or silicidewill be described in detail. First, among various possible metals, thecase of using Pt as the gate electrode 213 will be described. A layer ofPt is formed over the silicon-based substrate 212, and a buffer layerand a hard mask layer are formed over the Pt layer. The buffer layer andthe hard mask layer include an oxide-based material and a nitride-basedmaterial, respectively. The hard mask layer, the buffer layer, and thePt layer are etched using an etch mask. As a result, the gate electrode213 having the profile as illustrated in FIG. 3B is formed over thechannel region of the silicon-based substrate 212.

Among various possible metal silicide-based materials, a method offorming the gate electrode 213 based on platinum silicide will bedescribed. A layer of Pt is formed over the silicon-based substrate 212,and etched using an etch mask to make a portion of the Pt layer remainover the channel region of the silicon-based substrate 212. A resultantstructure is then heat treated to allow a reaction between Pt from thePt layer and silicon from the silicon-based substrate 212, so as toproduce platinum silicide. A portion of the Pt layer that does not reactwith the silicon is removed. As a result, the gate electrode 213 isformed over the channel region.

Referring to FIG. 3C, although not illustrated, an insulation layer foruse in a spacer is formed over a resultant surface profile of the gateelectrode 213 and the silicon-based substrate 212. An etch-backtreatment such as a dry etching is performed on the insulation layer toform spacers 214 on both sidewalls of the gate electrode 213. Thespacers 214 are formed to prevent an electric short circuit eventbetween the gate electrode 213 and the subsequent source and drainregions 215. Any insulation material may be used for the spacers 214.For instance, an oxide-based material, a nitride-based material, or astack structure thereof may be used for the spacer material.

Referring to FIG. 3D, the aforementioned source and drain regions 215are formed in the silicon-based substrate 212 exposed by the spacers214. The source and drain regions 215 may include a conjugate materialbetween a transition or rare earth metal and silicon. For instance, thesource and drain regions 215 are formed as follows. A metal-based layeris formed over a resultant surface profile of the spacers 214 and thesilicon-based substrate 212, and heat treated to react with silicon froma region where the source and drain regions 215 are to be formed. As aresult, a silicide layer that is self-aligned by the spacers is formed.

In more detail of the formation of the source and drain regions 215, alayer including a transition or rare earth metal is formed over theresultant surface profile of the spacers 214 and the silicon-basedsubstrate 212, and a rapid thermal annealing (RTA) treatment isperformed thereon. The thickness of the above metal-based layer,reaction temperature, and time are adjusted to allow the silicidereaction to proceed until a bottom portion of the source and drainregions 215 reach an upper portion of the buried oxide layer 211. Aportion of the metal-based layer that does not react with the silicon isremoved by a cleaning treatment. For instance, a sputtering method isperformed inside a chamber using argon (Ar), or the resultant structureincluding the metal-based layer is cleaned by being dipped into asolution of hydrogen fluoride (HF).

In the case of fabricating an N-type device, the source and drainregions 215 may include a rare earth metal-based material having a highSchottky barrier to electrons. The rare earth metal-based material mayinclude erbium silicide. In the case of fabricating a P-type device, thesource and drain regions 215 may include Pt having a low Schottkybarrier to holes or platinum silicide.

For instance, in the case of using erbium silicide as the source anddrain regions 215, an Er layer is formed over the resultant surfaceprofile, and heat treated at about 500° C. to about 600° C. to make Erfrom the Er layer react with silicon from the silicon-based substrate212. As a result of this reaction, an erbium silicide layer is formed.In the case of forming the source and drain regions 215 based onplatinum silicide, a Pt layer is formed over the resultant surfaceprofile, and heat treated at about 400° C. to 600° C. to allow areaction between silicon and Pt, so as to form a platinum silicidelayer.

According to various embodiments of the present invention,silicide-based Schottky junctions formed as the gate electrode and thesource and drain regions. These embodiments illustrate one approach toovercome a decrease in saturation current, usually caused by parasiticresistance generated when shallow junctions (e.g., source and drainregions) are formed, and a difficulty in thinly forming a gateinsulation layer, both usually observed in minimizing MOSFETs based onthe conventional technology. Furthermore, a SBTT can be fabricated usingthe conventional MOSFET fabrication equipment, and thus, manufacturingcosts can be reduced. As compared with the conventional technology, theembodied SBTT technology allows skipping of several processes (e.g.,process of forming gate insulation layer), and thus, a simplifiedfabrication processes can be achieved. Since the embodied SBTT structureand fabrication method follow an operational principle based on thequantum mechanical physical law, the embodied method can be easilyapplied in various fields.

While the present invention has been described with respect to specificembodiments, it will be apparent to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the invention as defined in the following claims.

1. A Schottky barrier tunnel transistor comprising: a gate electrodeformed over a channel region of a substrate to form a Schottky junctionwith the substrate; and source and drain regions formed in the substrateexposed on both sides of the gate electrode.
 2. The Schottky barriertunnel transistor of claim 1, wherein the gate electrode comprises oneof a metal-based layer and a metal silicide-based layer, wherein themetal-based layer comprises one of a transition metal and a rare earthmetal, and the metal silicide-based layer comprises a material obtainedby conjugating the metal-based layer and the substrate together.
 3. TheSchottky barrier tunnel transistor of claim 1, wherein the source anddrain regions comprise a metal silicide-based material.
 4. The Schottkybarrier tunnel transistor of claim 1, wherein the source and drainregions comprise one of a metal-based layer and a metal silicide-basedlayer, wherein the metal-based layer comprises one of a transition metaland a rare earth metal, and the metal silicide-based layer comprises amaterial obtained by conjugating the metal-based layer and the substratetogether.
 5. The Schottky barrier tunnel transistor of claim 1, whereinthe substrate comprises one of a silicon-on-insulator (SOI) substrateand a bulk substrate.
 6. The Schottky barrier tunnel transistor of claim5, wherein the silicon-on-insulator substrate comprises: a supportsubstrate used to provide a mechanical support; a buried oxide layerformed over the support substrate; and a silicon layer formed over theburied oxide layer.
 7. The Schottky barrier tunnel transistor of claim6, wherein the source and drain regions are formed such that a bottomportion of the source and drain regions contacts an upper portion of theburied oxide layer.
 8. The Schottky barrier tunnel transistor of claim1, further comprising spacers formed on sidewalls of the gate electrode.9. The Schottky barrier tunnel transistor of claim 8, wherein the sourceand drain regions are self-aligned in the substrate by the spacers.